SP-2: Extending 4-bit SP-1 CPU with Addressing Modes and Interfacing Features on Logisim for Computer Architecture Education

Abstract

The Computer Organization and Architecture (COA) course often lacks practical activities to help students deeply understand CPU design. To address this, we present SP-2, a 4-bit CPU architecture designed and simulated using the Logisim logic simulator. SP-2 builds on the previously developed SP-1 by introducing significant enhancements, including 40 instructions (up from 33), 5 addressing modes (up from 3, adding Register Indirect, Based, and Based Indexed with Displacement), and Input/Output (I/O) interfacing capabilities, which were absent in SP-1. A comparison with educational CPU models—Mic-1, SEP, DLX, and SP-1—shows SP-2's extended support for ALU operations, branching mechanisms, and I/O interfacing, surpassing SP-1 in versatility. Additionally, SP-2 aligns with most Learning Outcomes (LO) outlined in CS2013 and CE2016 curricula, particularly the Interfacing and Communication outcome, which SP-1 did not support. Despite its limitations, such as the lack of stack support, SP-2 bridges the gap between theory and practical application, offering students a valuable hands-on learning experience in CPU design.

Conclusion

In this paper, we presented SP-2, an enhanced 4-bit version of the SP-1 CPU, designed for undergraduate Computer Organization and Architecture (COA) courses. SP-2 offers a comprehensive instruction set and real-world processor features while remaining simple for students to understand. However, limitations such as the absence of stack support, small 4-bit word size, and lack of advanced features like multiprocessing restrict its capability for complex tasks. Despite these challenges, the Logisim simulator enables step-by-step design, providing hands-on experience. SP-2’s modular design allows future extensions, such as increased word size, stack support, and pipelining, enhancing its relevance for advanced education. The architecture aligns well with most Learning Outcomes (LO) in ACM’s Computer Science and Computer Engineering curricula. Future work will enhance the SP-2 architecture by adding stack support, multi-cycle operations, floating-point instructions, expanded I/O capabilities, and assembler support, bringing it closer to real-world CPU designs. To validate its educational benefits, classroom trials and student feedback will be conducted, providing insights into its effectiveness in improving learning outcomes and advocating for its use in undergraduate courses.

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